Forum Discussion
Occasional ContributorWhy would these two clear on reads behave differently?
Well, that looks basically ok.
I would have to assume that input CS is only valid for a single clock cycle. Correct?
Or if CS is valid for more than one clock cycle then SPI_RD is only valid for one clock cycle.
Otherwise if CS and/or SPI_RD is present for two (or more cycles) the register will be read once, then cleared, then read again with the value zero.
Occasional ContributorThe clear-on-read blocks are driven by the 100MHz FPGA clock, and are triggered when the cs and the spi_rd flag are set. The switch case selects which register is read(and cleared), based on the address value (adr) received over SPI.
always @(posedge clk)
begin
if (cs==1) begin
if (spi_rd==1) begin
case (adr)
0: begin
spi_out <= status_reg;
status_reg <= (status_reg & 16'b1110000000110001);
end
1: begin
spi_out <= error_reg;
error_reg <= (error_reg & 16'b0000000000000000);
end
endcase
end
end
//data is loaded into status_reg and error_reg here
end
The spi_out register is loaded into the actual shift register before being transmitted. We are using Altera's SPI IP and have had no problems with it thus far.
