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JET60200's avatar
JET60200
Icon for Contributor rankContributor
6 years ago

WHY there're 2 addtional Brdiges between "PCIE Hard Code IP" and " EMIF DDR4 IP" in pcie desig ?

Hi, I have a technical question regarding of "pcie avmm -> ddr4" logic path in "QSYS Interconnection". When checking customer's PCIE AVMM Design for A10, I find their "PCIE -> DDR4" data path fo...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

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