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JET60200's avatar
JET60200
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5 years ago

WHY there're 2 addtional Brdiges between "PCIE Hard Code IP" and " EMIF DDR4 IP" in pcie desig ?

Hi, I have a technical question regarding of "pcie avmm -> ddr4" logic path in "QSYS Interconnection". When checking customer's PCIE AVMM Design for A10, I find their "PCIE -> DDR4" data path fo...
JET60200's avatar
JET60200
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5 years ago

Thanks @sstrell​ for detailed clarification.

Regarding of "Quartus Automatic Adding the internal bridge" vs "Customer defines the defined bridge", how could we compare and evaluate their performance difference, to decide which one to be used ? Do you have any idea ?

Thanks a lot ​

BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Sir,

From performance perspective, usually without the bridge is the best because the latency is decrease. The bridge is add for some other purpose like both master-slave clock use different clock domain, multiple master to single slave or vice versa. You may refer to the description of the bridge as explain in this document, all bridge added is for some purpose.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/edh_ed51007.pdf