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Altera_Forum
Honored Contributor
Honored Contributorwhy the waitrequest signal is always 0
hi,all.I wanna use an arbitrator for two frame buffer to access the DDR3 SDRAM (IP:DDR3 SDRAM Controller with UniPHY Device:cyclone V Tool:QuartusII 13.0).But I find the read_waitrequest and write_wa...
Altera_ForumHonored Contributor
Honored ContributorMy signal is waitrequest(not waitrequest_n),and it may asserted by '1',and I think it would be set to '0' when the slave at the state of IDLE,right?
