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Altera_Forum
Honored Contributor
Honored Contributorwhy the waitrequest signal is always 0
hi,all.I wanna use an arbitrator for two frame buffer to access the DDR3 SDRAM (IP:DDR3 SDRAM Controller with UniPHY Device:cyclone V Tool:QuartusII 13.0).But I find the read_waitrequest and write_wa...
Altera_ForumHonored Contributor
Honored Contributorhi,jenglee,thank you for your reply.My local_init_done is asserted but the waitrequest signal never deasserted,so I don't know how to do next step.And I haven't do any request after reset.
