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Altera_Forum's avatar
Altera_Forum
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12 years ago

why the waitrequest signal is always 0

hi,all.I wanna use an arbitrator for two frame buffer to access the DDR3 SDRAM (IP:DDR3 SDRAM Controller with UniPHY Device:cyclone V Tool:QuartusII 13.0).But I find the read_waitrequest and write_wa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hello, I am also struggling with the DDR3 UniPhy, I do have better luck that my waitrequest is deasserted most of the time except when I am hit with efficiency issue. From my debug, you should not pull read/write request until the waitrequest is cleared, this is especially true when local_init_done is just asserted, and/or after performed manual refresh. Hope this helps.