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TSS3's avatar
TSS3
Icon for New Contributor rankNew Contributor
5 years ago

Why RX part of C5GT XCVRs (Transceivers) do not work.

Hi, We are working with a board designed in-house. It hosts a Cyclone 5 GT FPGA, of whose 6 XCVRs, we use 4: 3 RX @ 1485MbpS, and 1 RX&TX @4752MbpS. In some of these boards, the XCVRs work fi...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Itay,


Sorry for the delay. It seems like my response through email last week did not captured by the system.


Thanks for your update. For your information, you should also keep the reconfiguration controller in reset until the PLL output is stable. It is recommended for you to add some delay after the PLL achieve lock before releasing the reset to reconfiguration controller and Native PHY to ensure the PLL output is already stable.


Also, since the mgmt_clk is derived from IOPLL, you can also try to increase the frequency to 100MHz to see if there is any difference.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin