New Contributor
Regular ContributorHi Itay,
sorry for the delay. I might have overlooked this. As I understand it, you observe RX CDR does not achieve lock. Would you mind to share with me the Native PHY status signals in Signaltap when issue occurs ie rx_ready, sync status, CDR lock status and etc to see if there is any potential anomaly.
To help isolating potential signal integrity issue, it is recommended for you to create a simple duplex Native PHY design, send fix data from TX and enable internal serial loopback to RX to see if the CDR can achieve lock.
Just would like to check with you if the mgmt_clk to the reconfiguration controller is directly sourced from a free-running and stable oscillator on-board with frequency 75-125 MHz? This is to ensure the RX offset cancellation can be performed successfully during power up so that the transceiver can function correctly.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorHi Chee,
I can share the Signal-Tap only after the boards return to our offices.
They are being debugged now, on multiple other issues.
A loopback is possible only on the bidir XCVR (SFP) but not on the 3 RX-only XCVR,
as their TX counterparts are not routed in the PCB.
The mgmt_clk is 87.5MHz, but created from an FPGA-internal PLL.
The PLL itself is fed by a free-running and stable oscillator.
However, my design includes a mechanism supposed to keep the XCVR reset signal asserted,
as long as said PLL is not yet locked.
Thanks,
Itay
