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RDM's avatar
RDM
Icon for New Contributor rankNew Contributor
7 years ago

Why Gated clock design has better FMAX?

I've been reading "RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability" by Pong P. Chu. I'm in section 9.1.2 ("Misuse of gated clocks"), which explains that we should ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

The constraint should be create_clock -name clk -period 50MHz [get_ports {clk}]

Note that the result might vary even if the same design is compiled for several times due to different placement and routing.

Thanks.