Why does quartus think my signal is a clock?

One thing I see in the code is not a clear use of synchronization in your VHDL processes.

As a matter of code style, it might be appropriate to trigger the processes on the clk signal alone, unless you are purposely wanting an asynchronous design style. As others have said, Quartus infers latches, and your design will operate where values appear on the output of the latch, likely, within the current clock cycle. This may have unintended timing effects, and can set up unwanted feedback paths--even with the inserted latches.

Better, more robust style is to have the clk and reset signal in the sensitivity list of the 2nd process, and have the other signals references in conditional statements in the logic. This means all operations would be synchronous with the clock.

Then, you can use the clk'event attribute to control execution of statements in the process, like this:

if (clk'event and clk = '1') then

-- insert all the other process code inside this condition.

end if;

Hope this helps.

regds,

jim