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Altera_Forum
Honored Contributor
Honored ContributorWhy does quartus think my signal is a clock?
Here is the code snipped begin
write_register <= '1' when ((chipselect = '1') and (write = '1') and (byteenable = "1111") ) else '0';
process (clk,reset_n)
begin -- process
if reset_n...
Altera_ForumHonored Contributor
Honored ContributorYou delete the line:
out_register <= out_register but the inferred latch problem persists. You don't make any assigment when enable = '0'. If you need a combinational output try: if enable = '1' then for i in 0 to (N_CHANNELS_ANA - 1) loop for j in 0 to 3 loop out_register(i)(j) <= out_settings(i*4 + j); end loop; end loop; else for i in 0 to (N_CHANNELS_ANA - 1) loop for j in 0 to 3 loop out_register(i)(j) <= '0'; -- Dafault value. May be different. end loop; end loop; end if; If you want a registered output use the clock: if(clk'event and clk = '1' ) then if( enable = '1' ) then for i in 0 to (N_CHANNELS_ANA - 1) loop for j in 0 to 3 loop out_register(i)(j) <= out_settings(i*4 + j); end loop; end loop; end if; end if; Last code I used enable as a clock enable signal.
