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Honored Contributor
Honored ContributorWhy does my ddr2 not work sometimes?
Recently I have met a problem.My fpga is ep4ce115f23c8 and I use the DDR and DDR2 SDRAM High-Performance Controller IP core to control the DDR2 MT47H64M16HR. Usually it works well.But sometimes the ...
Altera_ForumHonored Contributor
Honored ContributorWhat board are you using? Some dev kit or custom made board?
Have you verified DDR2 memory with Altera example design? Have you checked that all your signals are asserted correctly (local_read_req, local_burstbegin, local_size ect...) when local_ready goes down? Yes, it is OK to provide clock to pll_ref_clk from external crystal. You have to set DDR2 IP core to same frequency as crystal.
