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Honored Contributor
Honored ContributorWhy does my ddr2 not work sometimes?
Recently I have met a problem.My fpga is ep4ce115f23c8 and I use the DDR and DDR2 SDRAM High-Performance Controller IP core to control the DDR2 MT47H64M16HR. Usually it works well.But sometimes the ...
Altera_ForumHonored Contributor
Honored ContributorHi vlrean,
I checked the problem,but when I asserted read request,the local_ready is high.When I send my read commands,there is no write commands.I send the read address sucessfully,all works well,but data don't come out.I want to read out 1024 data,but sometimes only come out hundreds of them,or no data come out.I get my pll_ref_clk from a external crystal which is 50MHz,am I right?Shall the pll_ref_clk come from a pll?
