seanw_skhms
Occasional Contributor
Occasional ContributorWhy does Agilex-F PCIe RP IP example design assign the P0 to PCIe lane#0-3 instead of lane#4-7 ?
One question about the port assignment in the Agilex-F PCIe RP IP example design.
The Agilex-F PCIe RP IP has four of RP x4 bifurcation, and only the P0 core is exported in the example design, whic...
Ok after understanding further by checking the ED Qsys (platform designer).
I can see the JTAG master component is connecting to P0 of the P-tile IP. By right it should connect to channel 4-7 based on table 57. However, we not sure why ED connects it to 0-3, I will check this with the internal team but will need some time.
However, for urgent sake, you can try the approach by using lane 4-7 for the example design. If not working, then we will give a try on other port (by changing the connection in the Qsys) or another lane on assignment editor.
