Forum Discussion
Occasional ContributorWhy does Agilex-F PCIe RP IP example design assign the P0 to PCIe lane#0-3 instead of lane#4-7 ?
Ok after understanding further by checking the ED Qsys (platform designer).
I can see the JTAG master component is connecting to P0 of the P-tile IP. By right it should connect to channel 4-7 based on table 57. However, we not sure why ED connects it to 0-3, I will check this with the internal team but will need some time.
However, for urgent sake, you can try the approach by using lane 4-7 for the example design. If not working, then we will give a try on other port (by changing the connection in the Qsys) or another lane on assignment editor.
Frequent ContributorHello Sir,
The Table 57 is the bifurcation mode which is not available yet for current quartus version with 4x4 configuration.
For non-bifur mode, you can assign the port0 to any lane. You can refer to figure 4/5 for better understanding.
seanw_skhmsHi,
I am getting more confused by your words now. What do you mean by “non-bifurcation mode”? Is it possible to use the ”non-bifurcation mode” and to map the P0 core to the lane#8-11 in the same RP 4x4 example design you sent me? If so, I would like to get a demo code.
What I learned before from Intel FPGA support, see the attached received message, is that the bifurcation modes shown in Table-57 are supported by the Quartus rev-20.2, which matches with the connection drawing shown in Figure-4.
I understood that the Quartus v20.2 does not support the full control over the “bifurcation mux” hardware. But it should be able to support the set of port bifurcation muxes shown by the Table-57.
Since the example design you sent me uses the 4x4 configuration, I still think that the P0 core can only be mapped to lane#4-7 (the lane#0-3 are used by P2 core) by the 4x4 bifurcation mode shown in the table-57.
Best Regards,
Xiao
