Why do I see termination logic option errors when I turn on design partitions?

Using QII 14.0. My design successfully compiles when I turn of design partitions. But when I turn on design partition I get following error -

Error (169172): Output pin "adc_sense[2]" specifies a Termination logic option setting of Differential, however, only Series termination is allowed for output pins.

This output is defined to be a tri-state in the top-level using verilog as -

assign adc_sense[2] = (adc_sense_en) ? adc_sense_wire[2] : 'bz;

Any ideas on how I can fix or work around this?

BTW, I have following constraint in the QSF -

set_instance_assignment -name OUTPUT_TERMINATION OFF -to adc_sense[2]

Thank you.

Best regards,

Sanjay