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mohamis's avatar
mohamis
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Why do I get the following relsult in my FIR filter output

Hello, I want to simulate my FIR filter in Verilog. But I get the wrong result. For example, when simulating a complete sinusoidal wave as input, I get the following result:   Here is...
  • FvM's avatar
    FvM
    3 years ago
    You are using logical right shift for signed variables which corrupts the sign bit. Try arithmetic shift.
Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you

Kshitij Goel