Why can't a CPLD/FPGA use VCCIO as Core Voltage?

Hi,

in "the early days", both (I/O and Core) were operated by 5VDC (standard TTL). As on CPUs in PC the core voltage reduction supports both - higher operational speeds (as the voltage difference between "0" and "1" is reduced, reducing the "change between levels" time) and lower power consumption as the charge to change between "0" and "1" is reduced as well. Thus "the lower the core voltage, the higher operational speeds and lower power consumption" is possible. That's the one thing on core voltage. As the "area" is quite small, there is few less noise problem than e.g. on external signals running with PCB traces "around the world", picking up all kind of noise...

This directly points to why the I/O voltage is higher - noise immunity and compatibility with existing external devices. Even these must accept e.g. LVTTL (3.3V signals) being mostly developed for TTL (5V) interfacing. Well there are still devices for TTL, requiring level shifters to be connected...

It's a sort of trade-off, isn't it. Lower voltage = higher speed, less power but (for external signals) higher noise susceptibility. Thus the best was to split I/O and core to get "best of both worlds". (even if this requires an additional voltage source).

(one additional benefit is that for correct decoupled voltages, noise on VCCIO caused by switching signals cannot have effects on VCCINT, thus no influence on core operation)

Regarding the I/O current... If you have ten LED connected to the pins with each one powered with 10mA, the CPLD would draw 10*10mA=100mA on VCCIO for these 10 LED - but be aware not to overheat the MAX in this condition...

Best regards,

Carlhermann

Thank you very much for an absolutely wonderful explanation!

It never occurred to me that the transition time from 0V to 1.8V would be much lower than 0V to 5V! And indeed, it's very clear to me now that separate VCCIO and VCCINT has huge benefits.

Regarding LEDs, I was just giving an example :). However, suppose the LEDs are switched on by a Serial In Parallel Out shift register. It's a 10-bit shift register and so can handle 10 LEDs.

My question is, the current for driving the LEDs will be taken from VCCIO, yes, but will the power for the shift register be taken from VCCINT?

On my (small) board, I have a Max V CPLD with a 8 bit shift register. I noticed that my meter showed 0A as the current draw for VCCINT but around 20mA for the VCCIO. The shift register wasn't toggling very fast (under a Hertz), so my guess was that my meter just isn't good enough to measure the small current drawn by VCCINT. Am I correct?

Also, going back to 10 LEDs with 10mA per LED. The Max V Handbook states that the max. current draw per pin is 25mA. However, does this imply that I can actually draw, say, 15mA or 10mA per pin simultaneously? I.e. can I draw a total of 100mA distributed across 10 pins or if my load is this large, I better have a transistor switching it?

Hi,

the power for operating anything except the I/O pin is taken from the VCCINT. ALTERA provides power estimation tools to calculate the VCCINT current required based on the operation frequency, number of cells switching, ...

I'm pretty sure that operation with those low frequencies are nearby static signals and that you would need a better current meter to measure the VCCINT current, it should be far less than mA giving a first guess...

The handbook gives the normal and max. operation characteristic, i.e. one pin can provide max. 25mA (I'm not sure that ten pins directly located to each other will allow 25mA per Pin...). At least this current is also part of the power calculation and this will also give you an estimation of the power loss generated in the MAX will be dissipated w/o forced cooling.

Last but not least - distributing e.g. 100mA required current load to 10 Pins in parallel requires either current balancing circuits or all pins must switch simultaneous. In case you connect "push-pull" in parallel, there may be conditions with some pins driving high and others already have switched to GND - which is a short circuit...

If you have to switch currents higher than the current one pin can handle it's better to connect an external transistor to decouple the signal (MAX) and the power (LED).

Best regards

You should review this Altera application note related to CPLD as LED drivers http://www.altera.com/literature/an/an286.pdf

If the permitted total VCCIO and GND currents are observed, there's nothing against driving a number of LEDS from FPGAs or CPLD directly. It's mainly a question of design optimization, I think.

MAX V predecessor MAX II has a built-in linear voltage regulator to generate VCCINT from VCCIO (a dual supply version is available as well). It can be still considered for low part count designs, although a small (SOT-23) external linear regulator for designs with low clock rate and respective low core power demand shouldn't be a problem. For minimal overall power consumption, a swiched-mode regulator should be preferred.