Which clock pin can feed transceiver without DQ pins limitation cycIVGX ?

Hi,

I am developing a custom board with 2 ddr2 x16 and a sata II (3,125Gbps) interface on a cyclone IV GX / F27 package.

I did this pinout:

- DDR2_a => bank8 / DQ3T x16

- DDR2_b => bank3 / DQ3B x16

- SATA RX/TX => GXB_RX4 / GXB_TX4

- Clk_125MHz_p/n => Ref_clk_3_n/p => use pll_8 as a MPLL and pll_2 as a GPLL

- Clk_50Mhz => bank4 => use pll_1 as GPLL

I use the same SATA configuration in my cyclone IV GX eval kit and it works (with a critical warning: input clock inclk[0] may have reduced jitter performance while used for transceiver channels that configured at a data rate that is higher or equal to 2.97 gbps because it is fed by a clock pin "pin_l15".).

But I am afraid that ddr2 won't work on my custom board. There is no compilation failure with this pinout for my custom board but I have just found in the cyclone IV pin connection guidelines that there is some restrictions for transceiver working at > 2.97 Gbps.

It says that if refclk2/refclk3 is used for feeding transceiver, you can not use bottom/top banks for x16 DDR (page11, http://www.altera.com/literature/dp/cyclone-iv/pcg-01008.pdf).

If I use closer input pins (ref_clk_4 or ref_clk_5) compilation fails…

So the problem is if I use ref_clk_3 ddr2 probably won't work and other clock pins don't work.

My need is to find a pinout to have:

- 3,125Gbps interface and its 125MHz dedicated clock input pin

- 2 ddr2 interface which fill only one bank per interface (I need most of other IOs for my design and they have different voltages).

Is it achievable?

Thanks in advance !