whether there is some component like IOdelay in Xilinx FPGA?

I think you do, but can't remember. The Stratix family has dedicated serializers and the timing report is automatic by running Report RSKM in TimeQuest. If that doesn't return anything, than you will want timing constraints. Note that the data and clock are coming in edge-aligned, so the FPGA needs to center-align the clock. The external clock is just a virtual clock, just at the 192MHz period. Then just do two sets of set_input_delay to say it is sending data on both the rising and falling edge:

set_input_delay -clock virt_192 -max 0.0 [get_ports {din[*]}]

set_input_delay -clock virt_192 -min 0.0 [get_ports {din[*]}]

set_input_delay -clock virt_192 -max 0.0 [get_ports {din[*]}] -clock_fall

set_input_delay -clock virt_192 -min 0.0 [get_ports {din[*]}] -clock_fall

Change the -max and -min values to show how much skew there is on the data. Note that your setup relationship should be half_data_window and hold relationship should be -(half_data_period). (This is all if report_rskm doesn't return anything, which I don't think it will)