whether there is some component like IOdelay in Xilinx FPGA?

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The altiobuf has a dynamic delay chain that can be configured(Stratix family). Most people do NOT use it like Xilinx. For Altera devices, if you put in timing constraints it will set the IO delay chain to the best value for margin across PVT. Also, you can force it with assignments in the Assignment Editor, such as D2 Delay Chain... (There are multiple delay chains for some of the I/O, so be sure to look in the handbook). But probably 95% of users just do I/O assignments, 4% force the delay chain to values in the Assignment Editor, and less than 1% dynamically modify it. What is it you're trying to do?

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I do design with 384mbps serdes interface.(look the attachment)

And I had used the IP core below.

altlvds_rx_component : altlvds_rx

GENERIC MAP (

common_rx_tx_pll => "ON",

deserialization_factor => 12,

implement_in_les => "ON",

inclock_data_alignment => "UNUSED",

inclock_period => 31250,

inclock_phase_shift => 0,

input_data_rate => 384,

intended_device_family => "Cyclone IV E",

lpm_hint => "CBX_MODULE_PREFIX=lvds_rx",

lpm_type => "altlvds_rx",

number_of_channels => 8,

pll_self_reset_on_loss_lock => "OFF",

port_rx_channel_data_align => "PORT_USED",

registered_data_align_input => "OFF",

registered_output => "ON",

use_external_pll => "OFF"

)

PORT MAP (

pll_areset => pll_areset,

rx_inclock => rx_inclock,

rx_cda_reset => rx_cda_reset,

rx_in => rx_in,

rx_channel_data_align => rx_channel_data_align,

rx_locked => sub_wire0,

rx_out => sub_wire1,

rx_outclock => sub_wire2

);

the Fck is used as rx_inclock.

At this case,is there need to add timing constraints?