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Altera_Forum's avatar
Altera_Forum
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14 years ago

Where can i find the time diagram of HY57V561620T-H?

Hello,

i have a fpga board with a hy57v561620t sram chip, i want to write a sram controller, but i can not find the time diagram, i wonder know how it works?

help please!

(i known it's easy to make it work with nios and it's components, but i want to known how it works more than see the result)

regards.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    This is what I found at the top of a google search: http://www.ic72.com/pdf_file/h/185830.pdf It's a bit odd that they don't include timing diagrams though so I would assume it's a data and address phased aligned interface similar to the SSRAM component in SOPC Builder. I'm guessing if you used that component in the 3 cycle latency mode and set your .sdc constraints accordingly you should be able to make this memory work.