Altera_Forum
Honored Contributor
14 years agoWhat's wrong in my design?
Hi,all
I have develop a system with two FPGA. the one is EP3C10 and the other is EP3C25. I config them by Multi device AS mode. the connect scheme is followed Figure9-4 of handbook of page175 Two different sof file must be loaded to them separately.the sof corresponding to the master device is come out by AS compiling. the sof corresponding to the slave device is come out by PS compiling. Now I convert two sof file into a pof file and then loaded into EPCS16 but neither of them work. After configuration, the message window of QuartusII will not show any error or warning. the nCEO of master device will not assert to low. then I configurate the master device only by separate the board trace of shared config_done and configuration is successful. What's wrong in my design? hope your good solution!