Forum Discussion
Deshi_Intel
Regular Contributor
6 years agoHi,
At high level based on error message, looks like you are placing transceiver Rx channel on a transceiver Tx channel pin location.
But to confirm, can you share out your Quartus design archived *.QAR file then I can help you to analyze the fitter error better ?
You can also checkout below link on transceiver channel placement guideline for Stratix 10 FPGA.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an778.pdf
Thanks.
Regards,
dlim