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SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

What's the proper DDR4 termination method in Intel FPGA?

My design contains a DDR4(discrete component) EMIF, and I terminate the address/command/clk in the same way with Arria10 development kit DDR4 daughter card(DIMM). Here're my questions: The address...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi SYiwe,

Thank you for the diagram and sorry for the confusion. My bad, I was not referring to FPGA output clock at first.

Yes, the CK0_T/CK0_C should be terminate pull-up to VTT. You need to follow the terminationguidline based on the I/O standard you used.

Regards,

Aida