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Honored Contributor
Honored ContributorWhat's LVDS Setup and Hold time?
Hi, So i've read this Setup and Hold time specification from a datasheet for an ADC. I am not sure what's the meaning of it, but I am assuming that the setup and hold time for the FPGA must be ...
Altera_ForumHonored Contributor
Honored Contributorrbugalho is absolutely right on this. The ADC setup and hold time is a constraint of not just the clock/data to output of the FPGA pins but a consequence of the path delay of each of those on the PCB board. Therefore, you need to specify the constraints of delay and clock to output from the FPGA including all the PCB path constraints etc so you can meet the setup of the ADC inputs.
