What's LVDS Setup and Hold time?

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Hi,

So i've read this Setup and Hold time specification from a datasheet for an ADC. I am not sure what's the meaning of it, but I am assuming that the setup and hold time for the FPGA must be higher than the setup and hold time requirement for the ADC's LVDS in order to receive the data from ADC properly.

Am i right on this? or is it the other way around.

Thanks.

Michael

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The set-up and hold time given by the ADC's data-sheet specify what you are going to get at a minimum (from the ADC). You use these to make up the set_input_delay constraints for TimeQuest to guide the fitter, and to chcek the results of the compilation. On a successful compilation TimeQuest will report (considerably) shorter set-up and hold times needed by the FPGA.