Altera_ForumHonored Contributor15 years agoWhat's LVDS Setup and Hold time? Hi, So i've read this Setup and Hold time specification from a datasheet for an ADC. I am not sure what's the meaning of it, but I am assuming that the setup and hold time for the FPGA must be ...Show More
Altera_ForumHonored Contributor15 years agoI guess this will be help. http://en.wikipedia.org/wiki/flip-flop_(electronics)
Recent DiscussionsMAX10 Bitstreams AuthenticationArria 10 GX RX max intra-differential pair skewCyclone 10 GX development board collateralsAgilex 7 FPGA Availability on Cloud Platforms (AWS, Azure, GCP)?AGRW027R28A2I2V Thermal Model