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Altera_Forum
Honored Contributor
18 years agoAltera documents state that the board layout for rrefb resistor must be very clean. Any noise introduced from the board layout can affect transceiver performance. As suggested earlier, gluing resistor through thin wires to the board pin can be an option, but it might affect transceiver performance.
As for the reference clock, transceiver refclk usually has strict input clock jitter requirements. Usually, output clocks from the FPGAs are not as clean as required by the high speed transceivers. One option is to bring those clocks out of the FPGA and clean them through some external clock buffer, before feeding it to high speed transceiver clock pin. AC coupling is required for Altera Transceiver clocks, except for the PCIe clock.