Forum Discussion
SK_VA
Occasional Contributor
Occasional ContributorWhat timing constraints can be given for setting clock skew from FPGA input to PLL output between two similar boards in a system?
Hi, I have a 100 MHz clock fed to FPGA on board from an external board.Two similar boards are present in the system.Same 100Mhz clock is fed to both boards on the system.This 100MHz clock is input t...
SK_VAOccasional Contributor
Occasional ContributorSo there is no ways to constrain this clock path?
Can I set clock uncertainty constraints?
