Forum Discussion
SK_VA
Occasional Contributor
Occasional ContributorWhat timing constraints can be given for setting clock skew from FPGA input to PLL output between two similar boards in a system?
Hi, I have a 100 MHz clock fed to FPGA on board from an external board.Two similar boards are present in the system.Same 100Mhz clock is fed to both boards on the system.This 100MHz clock is input t...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
If the pin location for the source (FPGA input pin) and the PLL are the same in both boards, the clock delay will be the same since the boards are the same.
Thanks
SK_VAOccasional Contributor
Occasional ContributorBut the pll in both boards may not lock at the same.There might be skew in the clock output from PLL in these boards if the PLLs gets locked at different instant.
Also these boards might be in different PVT conditions that might contribute to the skew.
