Forum Discussion
SK_VA
Occasional Contributor
Occasional ContributorWhat timing constraints can be given for setting clock skew from FPGA input to PLL output between two similar boards in a system?
Hi, I have a 100 MHz clock fed to FPGA on board from an external board.Two similar boards are present in the system.Same 100Mhz clock is fed to both boards on the system.This 100MHz clock is input t...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
Does this mean that you have one clock source to be fed into two different designs? If you want to set data path skew in one design, you may use set_max_skew
Reference: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_sdctmq.pdf Page 2-58.
Thanks.
SK_VASame clock is fed to two different boards in a system that performs similar function.The FPGA program that runs on both boards are same.
I want to make sure the clock skew from the source(FPGA input pin)to PLL output that feeds my logic is within a range of ps. In hardware they have taken care that source clock reaches both FPGA at the same time. This is to make sure that the logic works on both FPGAs in different boards works concurrently without delay.
