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Honored Contributor
Honored ContributorWhat the relative timing relations between 2 clocks out of the PLLs？
Hi all: I have a question about PLL’s output clocks. In my project, the input clock is 100MHz. I generate a 387.5MHz clock using PLL with multiplying/dividing factor of (32/8), and anothe...
Altera_ForumHonored Contributor
Honored ContributorThe timing relation can be characterized by a defined initial phase on PLL reset. Due to the rational 8/19 frequency ratio of both outputs this isn't much better than unrelated clocks, I think.
P.S.: I reviewed your post and found that you are apparently talking about independent 20 and 100 MHz input clocks. In this case, theirs no timing relation between PLL outputs of course.
