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Altera_Forum's avatar
Altera_Forum
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12 years ago

What is the suitable Voltage level for clock input? Vccio , Vccd_pll ?

I'm designing board with cyclone IV, so i was checking several reference designs, and I looked in the Cyclone III LS FPGA, in this design the designer set the bank 7 and bank 8 with a Vccio=1.8 (the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thank you very much for your answer,already I have it clearly, but i have a query, it's a alittle bit out of topic, the FPGA that I using is EP4CE75F23C8, it's the comercial applicaion, but if i decide change to EP4CE75F23I8 (industrial application), change the pins position or only changes thermal characteristics?

Thanks