Honored Contributorhi:
For example, after CycloneIV device power up, what is the initial value of the internal registers? I found a interesting thing: usually,we set the initial value for the registers like this: always@(posedge clk or negedge reset) reg <= 0; But when you trace the reset signal to the most original, it would be pure controlled by the FPGA hadrware itself instead of verilog statement.
Honored ContributorRegisters will usually power up to '0' unless otherwise specified with an initial value or async reset
Honored ContributorThanks for your reply. Dose this mean the verilog statement like : always(posedge clk or negedge reset) rega <= 1 will force the FPGA to load the rega to logic 1 as soon as power up, even the external reset hardware dose not active?
Honored Contributorwhat that case, it is unlikely to create a register for rega as it is always driven to 1.
but in the following case it should:
always @(posedge clk or negedge reset) begin
if(reset == 1'b0 ) rega <= 1'b1;
else rega <= ip;
end
sorry for my provious reply. let me update as below:
If I use always@(posedge clk or negedge reset) begin if(!reset) rega <= 1; else rega <= in_a; end Dose this mean the FPGA will force the FPGA to load logic 1 to rega as soon as power up, even the external reset hardware dose not active?Honored ContributorIs this done by the synthesis tool or need to config something else?
Honored ContributorHonored ContributorRoger that! Also I have seen the statement like: reg[15:0] cnt = 16'd0; in the source code. Does this has the same effect to load 16'd0 to cnt as soon as FPGA power up? The complete code is shown as below:
module reset( input clk, output rst_n ); reg[15:0] cnt = 16'd0; reg rst_n_reg; assign rst_n = rst_n_reg; always@(posedge clk) if(cnt != 16'hffff) cnt <= cnt + 16'd1; else cnt <= cnt; always@(posedge clk) rst_n_reg <= (cnt == 16'hffff); endmodule These is no async reset in the code and this module is dedicated to generate system reset to other modules. As this purpose, the cnt must be 0 aftera power up to generate the rst_n. Is my understanding correct?Honored Contributor
