What is the maximum clock frequency input (CLK0p) for a Max10 single supply voltage(10M02SCU169I7G)?

Thanks a lot.

It says in the note "This parameter is limited in the Intel Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard."

Do I have to compile the hole design to be able to see this or is there some other way?

I'm designing the hardware now and want to make sure that the device can handle the input frequency before starting to compile/program fpga.

Thanks

Anders