Honored ContributorIs the CPLD device used to store the FPGA configuration for the booting the bitstream dumped into the EPCS flash device? (Switching/control logic stored in the CPLD??)
The rotary switches provided in the dev board is such, each position relates to different object file images stored in subsequent locations. Thank you for your time.
Honored ContributorWhat does the documentation say?
Honored ContributorIf it's similar to my Cyclone IV board, the MAX chip is part of the USB Blaster. At first glance it looks like it's mostly for voltage level conversion and maybe serial/parallel. It think there are some USB JTAG example circuits floating around on the internet, you might do some searches.
Honored ContributorYou don't say which Cyclone III dev kit it is. However, as Galfonz states - it's probably part of the on-board USB-Blaster circuitry. If so, it shouldn't appear in the JTAG chain when you scan it.
However, if it does appear in the JTAG chain when you scan that it's more likely to be a 'system controller' and, as you suggest, may be used to select which image to boot the FPGA from. An example of this can be found on the cyclone iii ls fpga development kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyc3-ls.html) and other, generally newer kits. Cheers, AlexHonored ContributorI'm not sure which Cyclone III dev kit you are referring to but the Cyclone III dev kit is not built with EPCS device. Typically there is a CFI flash device populate on the dev kit. The MAX II device on the dev kit work as the system controller on the board to perform the FPGA configuration, programming flash, clock and power monitoring and others. You can refer those information from the reference manual in the dev kit installation folder.
