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Altera_Forum's avatar
Altera_Forum
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12 years ago

what is the difference between the sampling and clock frequency about FIR filter

hi,everyone.i want to ask whether the frequency of sampling and clock need to keep the same in use of fir compiler. according to my understanding,if they don't keep the same,the processing data rate ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

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Thank YOU.when we use fir compiler,we need set the value of Fs.so, i want to know that is it necessary that Fs must be equal to the front AD's sampling frequency.the Fs decides what performances about FIR .besides, is it have effect on data transmission? for example, the AD's sampling frequency is 100MHZ,signal's bandwidth is 40MHZ,which value i need choose for the Fs and clock frequency about FIR filter.

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If your adc is sampling the signal at 100 Msps then this is Fs of your stream.

The clock can be 100MHz or multiple. I will assume you already have the ADC clock of 100MHz so just use it in FPGA