What is the best HDL language for the future: VHDL, Verilog or System Verilog?

Verilog is a subset of System Verilog. The distinction is mostly that the subset which is understood by synthesis tools is mostly (old style) Verilog since SystemVerilog was mostly extensions to Verilog at the test-bench level (and the synthesis tools are usually old). I.e. you won’t get a different simulator/language, you’ll just be dealing with a different subset of SystemVerilog.

What industry needs (for DUT level design & test) is something that actually handles more abstractions and understands power properly. Verilog-AMS (which is a different standard) actually does a lot of the power stuff, but the SV guys hate all things analog and have not integrated it (and have no real plan to do so).

What the test-bench guys need is actually better C++ support so you can reuse your tests in production environments (after your chip is fabbed). The SV guys don’t like that either since it would be free.

The future will probably be asynchronous design methodologies done with C++, but in the meantime verification with SystemVerilog is in demand.