Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorWhat is the best HDL language for the future: VHDL, Verilog or System Verilog?
Hello, which language is the best to learn for the future of FPGA design Verilog, VHDL or System Verilog? Or, is there something else that will replace the current languages? thanks, joe
Altera_ForumHonored Contributor
Honored ContributorI typically code in VHDL due mainly to the fact that when I had to make the language selection, Altera MAX+Plus II's Verilog support was lacking a feature I needed.
If put in the same position again, I would note that all of Altera's recent IP cores are being written in SystemVerilog (or perhaps Verilog). Mentor Graphics "Verification Academy" https://verificationacademy.com/ has a whole lot of resources on learning the correct way to code in SystemVerilog, and there's a couple of decent books on the subject SystemVerilog for Verification, Spear SystemVerilog for Design, Sutherland et al. You can also download the SystemVerilog specification for free. http://standards.ieee.org/getieee/1800/download/1800-2012.pdf So, although I'm still stuck in my ways and will continue to code in VHDL, I do see the advantage in learning SystemVerilog, and coding in whatever is appropriate for the particular task. Cheers, Dave
