Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

What is the best HDL language for the future: VHDL, Verilog or System Verilog?

Hello, which language is the best to learn for the future of FPGA design Verilog, VHDL or System Verilog? Or, is there something else that will replace the current languages? thanks, joe
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

From what Ive seen, VHDL tended to be used more by FPGA guys, with verilog used for both ASIC and FPGA. System verilog is only really useful as a verification language at the moment. But VHDL is getting a lot of features that make it match the power of System Verilog for verification, and theres seems to be a big push to get more people to use VHDL.