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SJadh1's avatar
SJadh1
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7 years ago

What is rx_pma_iqtxrx_clkout signal ?

Hello, I am working on a design with transceiver. I would like to know what is rx_pma_iqtxrx_clkout signal ? What are the usage scenario's of rx_pma_iqtxrx_clkout signal ? Thanks & Regards, Sach...
Deshi_Intel's avatar
Deshi_Intel
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7 years ago
Hi Sachin Jadhav, Using FPGA core clock network is expected to be bad as compared to dedicated refclk pin as clock source of fPLL. The clock control block debug is the only idea that I have. Unfortunately I am not the right expertise and not that familiar with fPLL loose lock issue. May I suggest for you to file new Forum case and make the title clear to be "fPLL loose lock debug help request" ? Then perhaps some other more experience fPLL user can jump in and help you out. Thanks. Regards, dlim
  • SJadh1's avatar
    SJadh1
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hello Dlim,

    I tried the clock control suggestion, but it didn't worked.

    I have also filed a new Forum case for fPLL lock issue.

    Your help is appreciated.

    Thanks & Regards,

    Sachin Jadhav