What is rx_pma_iqtxrx_clkout signal ?

Hi Sachin Jadhav, In general, below is the common cause of PLL loose lock issue. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/support/devices/pll/pll-loss-of-lock-checklist.pdf Looks like your fPLL loose lock is highly caused by the instable or noisy rx_pma_iqrxtx_clkout as fPLL clock source. May I know does fPLL loose lock in CDR LTD or LTR mode ? I presume LTR mode should still generate stable clockout and it shouldn't cause fPLL to loose lock, right ? If everything works correctly then alternate debug suggestion is to constraint rx_pma_iqrxtx_clkout clock network to minimize the clock jitter. You can try to connect rx_pma_iqrxtx_clkout to "clock control block" IP and configure it to regional clock network instead of global clock network if possible. Thanks. Regards, dlim