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SJadh1's avatar
SJadh1
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7 years ago

What is rx_pma_iqtxrx_clkout signal ?

Hello, I am working on a design with transceiver. I would like to know what is rx_pma_iqtxrx_clkout signal ? What are the usage scenario's of rx_pma_iqtxrx_clkout signal ? Thanks & Regards, Sach...
Deshi_Intel's avatar
Deshi_Intel
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7 years ago
Hi Sachin Jadhav, So in short, you are seeing expected behaviour in CDR AUTO mode and CDR Manual LTR mode but not on Manual LTD mode, right ? 1) CDR AUTO mode - rx_is_lockedtodata is toggling (expected with no incoming Rx data) 2) CDR Manual LTR mode - rx_is_lockedtoref stay high (expected result) 3) CDR Manual LTD mode - rx_is_lockedtodata stay high (not expected due to no incoming Rx data) May I know are you following "Resetting the Transceiver in CDR Manual Lock Mode" guideline as per below link, page 431 ? https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf Can you share with me your signal_tap screenshot vs expected reset sequence timing diagram in Figure 206 ? If you are using transceiver toolkit, then you can perform serial loopback or external loopback on board via SMA cable. Directly use toolkit PRBS pattern generator to test the data traffic and CDR lock status. It's recommended to test CDR with incoming data traffic instead of no traffic condition. You can also share with me your toolkit screenshot result if you have it. Thanks. Regards, dlim
SJadh1's avatar
SJadh1
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7 years ago

Hello Dlim,

I have gone through "ug_arria10_xcvr_phy.pdf"

The reset sequence suggested by you is important from reception/transmission of data.

My test scenario is about clock generation, that too specifically about CDR block.

I want to understand why CDR block generates 31.38 Mhz clock if no input is present on Rx lane and rx_set_lockedtodata is high ?

This is important because in my design I will be using RX pma clock as a reference clock to a fPLL instance.

For better understanding if you could share below things it would be helpful.

1) Block diagram listing out analog block and digital blocks.

2) Various reset signals controlling analog block and digital block.

3) AC-DC Characteristics of each analog block.

4) Input-Output specification of each digital block.

Thanks & Regards,

Sachin Jadhav