Forum Discussion
Hi Sachin Jadhav,
Pls see my reply below
- Did you check CDR lock status ?
- The best way to ensure CDR is working correctly is to check on "rx_is_lockedtodata" or "rx_is_lockedtoref" signal depend on which CDR lock mode you are using
- What's the lock status when you set it to either LTR mode or LTD mode
- Confirm CDR lock mode is setup correctly
- Sorry, your explanation on CDR lock mode setting is unclear to me. Can you confirm are you setting it correctly as per below attached pic ?
- I presume you are getting 50.625MHz when you set it to lock to ref (LTR) mode and got 31.38MHz when set it to lock to data (LTD) mode. I suspect your on board incoming data is transferred at around 1Gbps instead of 1.62Gbps.
- fPLL should lock if rx_pma_clkout is stable and output correct frequency
Thanks.
Regards,
dlim
Hello Dlim,
During entire test scenario there is not data coming on rx lane of serdes. Basically no external wire is connected to entire serdes port.
Below is my observation.
1) When CDR is set to LTR mode, rx_is_lockedtoref is getting set and I am seeing 50.625 Mhz clock from rx_pma_clkout.
2) When CDR is set to LTD mode, rx_is_lockedtodata is getting set and I am seeing 31.38 Mhz clock from rx_pma_clkout.
As my rx lane of serdes is not receiving any data why does CDR locks when set to LTD mode and outputs 31.38 Mhz clock ?
For this experiment I have used Arria 10 transceiver toolkit and modified IP instances for required data rate.
I have also edited top level so as to observe clock and control signals on sma connector for debugging.
Thanks & Regards,
Sachin Jadhav