What is rx_pma_iqtxrx_clkout signal ?

Hello dlim,

Thank you for responding.

I am cascading output clock(rx_pma_clkout) of RX PMA to the reference clock of fPLL instance so as to generate transmit clock.

I have configured RX PMA CDR to use local on-board reference clock as source. Local reference clock frequency is 108Mhz.

Transceiver is configured with Data rate is set to 1.62G and Data width is 32bit in PCS direct mode.

I am manually controlling RX CDR.

Below is my observation.

1) When rx_set_locktodata, rx_set_locktoref is 2'b00, I see a very jittery clock on rx_pma_clkout.

2) When rx_set_locktodata, rx_set_locktoref is 2'b01, I see a very clean 50.625 Mhz clock

3) When rx_set_locktodata, rx_set_locktoref is 2'b1X, I see a very clean of 31.38Mhz (What is the source of this clock)

In my test setup as of now I don't have any high speed data reception on serdes.

Why CDR is outputing 31.38 Mhz when rx_set_locktodata, rx_set_locktoref is 2'b1X ?

I also don't see my fPLL instance getting locked, when I set CDR to rx_set_locktodata, rx_set_locktoref is 2'b01.

Do I need to calibrate PLL for getting locked whenever there is change in rx_set_locktodata and rx_set_locktoref combination ?

Thanks & Regards,

Sachin Jadhav