New Contributor
Super ContributorHi Christian,
Thank you for contacting Intel community.
If you are referring to the pad size of pin 144, in the link you have given, "D2 and E2" are the exposed pad size.
If not, please explain which of the pad size are you referring to?
Sorry to let you know that Intel FPGA do not provide support for PCB footprint symbols for FPGA and CPLD device families, similar to configuration devices.
However, we will continue the support by providing the schematic symbol which you can download from the link above. You could have the schematic symbol in .olb format from the link below:
https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/pcb/pcb-cadence.html
Regards,
Aim
New ContributorHello @Aiman.N_Intel
i am not asking about dimensions indicated in the documentation, which i know already, but about your recommended effective dimension for the Pad on the PCB.
We need to reduce any kind of possible issue related to soldering.
I need Intel's suggestion about how much make the Pad bigger or smaller with respect of the nominal size indicated in the datasheet and even considering any tolerance needed.
Can you please let me know suggestions, indications about how to properly size the PCB pad to eliminate or reduce as much as possible any kind of issue related to reflow soldering.
I hope now the request is more clear.
For example we are worried about how avoiding the risk that solder paste remains floating under the component and not soldered properly on the exposed pad which is not a visible problem with optical inspection (X-Ray inspection would be mandatory).
Not all manufacturers we work with can do x-ray inspection and therefore we would like to find a solution to avoid x-ray inspection still with guarantee of correct soldering of the FPGA component.
Thank you very much hoping in your reply soon,
Best Regards
Christian
