Honored ContributorHi
I'm brand new to cpld and starting with a max v eval board. In the installation folders there is a project called golden-top. I can't find any proper explanation of it any where on the internet or altera website or these forums. any body know? thanks
Honored ContributorIts a top-level design for the evaluation board.
If you look through the installation for the board, you will likely find a schematic. Look at the schematic and look at the names in golden_top.vhd (if its VHDL) or golden_top.v (if its Verilog). If it really is a golden file, then it should have *all* pins that are assigned in the schematic included as port names on the golden top design. A top-level file is *not* sufficient to perform a hardware test. You also need a pin assignments file that tells Quartus what pins to use for what signal names on the golden top design. You may also need I/O constraints for voltage, slew-rate, pull-ups etc. Take the time to review the golden top design with respect to the schematic. Don't be surprised if you find discrepancies in the golden design. I will typically take a golden design and print out the schematic, and then check all of the pins have been defined - I then add the ones that the golden design misses. Cheers, DaveHonored ContributorI didn't find any link to search this phrase.. Please show me here any specific link to understand that this a is top-level design for the evaluation board. Thanks in advance.
Honored Contributor
