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MTuck8's avatar
MTuck8
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6 years ago

What files to version control of PLL IP entity?

I need to add a PLL entity to my otherwise very portable & clean VHDL code. When using the Quartus IP library wizard to create a PLL I end up with about 10-20 files​ in my projects some of which loo...
MTuck8's avatar
MTuck8
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6 years ago

That does not sound like a good solution for an active open source project​ (you want all files to be in source form / plain text).

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Is there no pure HDL solution for instantiating a PLL? For instance, block RAM and DSP functions (multiplication) can be infered from regular HDL constructs. An Intel library of common IP (e.g. a PLL) would be very useful.

MTuck8's avatar
MTuck8
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6 years ago

So I found an HDL-only solution that worked for me, but it feels like a hack since the API seems to be undocumented.

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It's based on the concept of instantiating an "​altera_pll" module in parameterized Verilog, and then wrap it in a VHDL component.

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Source code here:​

https://github.com/mbitsnbites/fpga-ip/tree/master/pll

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I have no idea how well it works between devices and Quartus versions.​