New Contributor
Frequent ContributorHi ,
You can Qar the project file and can share with other designers, the Qar file have all the settings and design file.. For making Qar from Quartus follow the below procedure.
Click Project in Quartus submenu Archive Project.
New ContributorThat does not sound like a good solution for an active open source project (you want all files to be in source form / plain text).
Is there no pure HDL solution for instantiating a PLL? For instance, block RAM and DSP functions (multiplication) can be infered from regular HDL constructs. An Intel library of common IP (e.g. a PLL) would be very useful.
New ContributorSo I found an HDL-only solution that worked for me, but it feels like a hack since the API seems to be undocumented.
It's based on the concept of instantiating an "altera_pll" module in parameterized Verilog, and then wrap it in a VHDL component.
Source code here:
https://github.com/mbitsnbites/fpga-ip/tree/master/pll
I have no idea how well it works between devices and Quartus versions.
New Contributorperhaps creatr one set of IP files for every version of Quartus, and add them all to the Git repository?
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