Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHere is what is essentially my code... theres a bunch missing but this is the critical path:
in module A: assign reset_out = 1'b0; in module B: assign c_reset = reset_out always @(posedge clock or negedge reset_n) if (!reset_n) c_state <= IDLE; else if (c_reset) c_state <= RESET; else c_state <= n_state; from there, we do a d_state (delayed state) of c_state and do: assign phy_reset = (c_state == RESET) && (d_state != RESET); then fan out phy_reset to a bunch of FFs for synchronous clears. The problem comes where I would hope the state machine optimizer would reduce the states and ignore the RESET state. If I go into timequest, I can run a timing report through phy_reset and come up with valid paths